Technical Field
The present invention generally relates to fabrication of semiconductor devices. More particularly, the present invention relates to metallization of semiconductor devices at the Back End of the Line (BEOL).
Background Information
As semiconductor device size continues to shrink, making real-world electrical connections to the smaller feature sizes at BEOL also becomes more challenging. Known generally as metallization, a number of layers may be used. For example, copper voids can seriously impact device yield. To get good copper seeding and reduce the copper voids, a cobalt and/or ruthenium liner is used. However, current copper planarization processes include chemicals that attack the liner, resulting in post-planarization corrosion, creating a divot or void. The divot/void can cause reliability issues and device degradation.
Thus, a need continues to exist for reduced liner corrosion during metallization of semiconductor devices at BEOL.